Advanced focal plane arrays (FPAs), such as infrared focal plane arrays (IRFPAs) utilize embedded ADCs on the read out integrated circuitry (ROIC) die. On-ROIC digital readout allows on-chip digital signal processing, increased dynamic range, and increased signal to noise ratio. On-ROIC ADC is often incorporated at one or more FPA outputs or at ROIC columns. More ADCs on the ROIC tend to provide increased digital resolution and reduced ADC power due to reduced digitization frequency.
One serious limitation of current ROIC technology is the difficulty of achieving very large charge capacity in small pixel pitch. Analog circuits do not scale well because voltages and capacitances are reduced and transistor noise increases for smaller technologies and sizes. There have been efforts to overcome these analog limitations by implementing an A/D converter in each pixel, but those we are aware of have significant problems with high noise, large power dissipation and require extremely expensive non-recurring costs for very small design rule CMOS tooling. The ADC per pixel concept (also referred to as a digital pixel sensor (DPS)) has increased difficulty of implementation in large format mega-pixel FPAs as pixel pitch is reduced (<30 μm), ADC resolution increased (>14-bits) and FPA frame rate is increased (>60 Hz).
In-pixel ADC can be accomplished by counting charge packets integrated on CINT from the detector current Idet. In FIG. 1A, prior art, the photocurrent, created by the illumination, discharges CINT until Vint equals Vth (also referred to as Vref), then the comparator commands the injection of Q0 at the integration node and the counter is incremented by one. At the end of the integration time, the counter contains the number N. Since the LSB value of the A/D conversion is Q0, N·Q0 has been detected. In FIG. 1B, prior art, the charge packet reset is replaced by a voltage reset. The only difference between the two techniques is the way Q0 is generated. In the “voltage reset” case, FIG. 1B, Q0=Cint·ΔV=Cint·(Vo−Vth) and consequently the LSB is highly dependent on Vth. This technique is thus very sensitive to the performance of the comparator but allows an efficient layout. In the “charge reset” case, FIG. 1B, Q0 is generated by a charge injector, thus it relaxes constraints on the comparator and on CINT precision, providing the charge injector has good performance.
Both techniques, in FIG. 1A and FIG. 1B, require a binary counter per pixel that can occupy a significant amount of the readout pixel area, especially for a large number of bits and small pixel pitch. The repeated voltage reset or charge reset of CINT adds additional temporal noise.
A two-step ADC has been utilized to reduce in-pixel counter size and reduce ADC power. FIG. 2 shows prior art where the first 11-bits are determined by a charge counting architecture at the pixel-level and the last 5-bits are determined by a column level ADC. As illustrated on FIG. 2, the pixel uses a pixel-level ADC technique that consists in counting charge packets so that, at the end of the integration time, the pixel counter contains a digital value proportional to the total integrated charge and the residue remains on the integration capacitance (CINT). In FIG. 2 the in-pixel comparator is used only for the 11-bit in-pixel ADC. Voltage reset on the integration node is utilized. The voltage reset of CINT to Vdd adds additional reset noise (kTCINT).
FIG. 3, prior art, shows a two-step ADC where the most significant bits (MSBs) are determined in the pixel and the least significant bits (LSBs) are determined by digitization of the residual signal integrated on CINT. The LSB residual signal A/D conversion occurs external to the pixel. In FIG. 3, charge reset is utilized. A FET and first switch are disposed in series between a dump capacitor and the integration node. A second switch operates to discharge the dump capacitor, and an output of the comparator controls both switches in opposition. Upon command of the comparator circuitry, the integration capacitor transfers a fixed amount of charge into the dump capacitor through an injection FET with Vg=Vref 2 operating in saturation.
In FIG. 3, the bottom of the dump capacitor may be connected to a special reference voltage, but ground can be used when layout constraints exist. The common potential Vcomm may differ between the integrating and dump capacitors. Noise is added at the end of every charge dump event.
In a preferred embodiment, the circuit of FIG. 3 operates in a 5-volt system, Vref1 is 3.3 volts, and Vref2 is 2.5 volts. The values of Cint and Cdump are chosen such that the voltage at the integration node Vint does not fall below 2.5 volts (Vref2). The repeated charge reset of CINT adds additional reset noise (kTCdump).